<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>GPU on Daniel Park</title><link>https://parxd.github.io/tags/gpu/</link><description>Recent content in GPU on Daniel Park</description><generator>Hugo</generator><language>en-US</language><lastBuildDate>Thu, 05 Feb 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://parxd.github.io/tags/gpu/index.xml" rel="self" type="application/rss+xml"/><item><title>CuTe-ly writing an SM86 SGEMM</title><link>https://parxd.github.io/posts/cute-ly-writing-an-sm86-sgemm/</link><pubDate>Thu, 05 Feb 2026 00:00:00 +0000</pubDate><guid>https://parxd.github.io/posts/cute-ly-writing-an-sm86-sgemm/</guid><description>&lt;p&gt;I know what you&amp;rsquo;re thinking. A &lt;code&gt;fp32&lt;/code&gt; GEMM in 2026? For Ampere??&lt;/p&gt;
&lt;p&gt;Yes, SGEMM is rarely ever used these days in the ML space given the massive compute throughput gap between CUDA and tensor cores. For reference, an A100 PCIe&amp;rsquo;s (now almost 6 years old) peak theoretical performance for &lt;code&gt;bf16&lt;/code&gt; is 312 TFLOPs/sec. and 156 TFLOPs/sec. for &lt;code&gt;tf32&lt;/code&gt;, while &lt;code&gt;fp32&lt;/code&gt; sits at a &amp;ldquo;measly&amp;rdquo; 19.5 TFLOPs/sec. With &lt;a href="https://docs.nvidia.com/deeplearning/performance/mixed-precision-training/index.html"target="_blank"
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&gt;mixed-precision&lt;svg class="h-3 w-3 flex-shrink-0" id="external-link" xmlns="http://www.w3.org/2000/svg" viewBox="0 0 24 24"&gt;&lt;path fill="none" stroke="currentColor" stroke-linecap="round" stroke-linejoin="round" stroke-width="2" d="M15 3h6v6m-11 5L21 3m-3 10v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6"/&gt;&lt;/svg&gt;
&lt;/a&gt; training and quantized inference being the norm, GEMM itself is practically never done in &lt;code&gt;fp32&lt;/code&gt; today.&lt;/p&gt;</description></item></channel></rss>